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Alliance's AS90L10208 is a HyperTransport-to-PCI-X Bridge that interfaces the new generation of HyperTransport-based microprocessors ( µ P) and microcontrollers ( µ C) to PCI or PCI-X based peripherals. It also connects HyperTransport based hosts ( µ P and µ C) to HT-based peripherals as part of a HyperTransport device chain.
The AS90L10208 from Alliance Semiconductor can be configured to support either single 64-bit PCI-X bus or two 32-bit PCI-X busses. The AS90L10208 implements two bi-directional 8-bit HyperTransport interfaces that provide 1600 MBps of bandwidth in each direction. Up to 31 devices can be daisy-chained to build higher capacity systems with multiple PCI-X busses and HyperTransport-based peripherals. A fairness algorithm allocates bandwidth among devices, thereby eliminating starvation of bridges at the end of the chain.
The AS90L10208 breathes new life into systems that are encumbered by the limits of Conventional PCI or PCI-X based fabrics. It reduces the time to market, design complexity and system costs of PCI-X and HT-based systems.
Features:
- Two bidirectional 8-bit HyperTransport interfaces.
- Up to 800MHz DDR (Double Data Rate) clock frequency for a peak bandwidth of 1600 MB/s simultaneously in each direction.
- Complies with Revision 1.05 of HyperTransport I/O Link Specification.
- 2, 4, and 8-bit link widths supported.
- Supports asymmetric link widths and frequencies.
- Implements a HyperTransport tunnel.
- Can be configured as a single-ended cave device with only one link active.
- Supports a double-hosted HT chain (host CPU on each port).
- Single 64-bit PCI-X bus or two 32-bit PCI-X busses.
- Device emulates two HT link devices (with virtual internal tunnel in dual PCI-X mode).
- Implements two independent sets of CSRs in dual PCI-X mode.
- PCI-X bus can also operate in Conventional PCI mode.
- Operating frequencies and modes of the two PCI-X busses are independently selectable.
- Supports 50, 66, 100 and 133 MHz clock frequencies in PCI-X mode.
- Supports 25, 33, 50 and 66 MHz clock frequencies in PCI mode.
- PCI-X mode complies to Revision 1.0b of PCI-X Addendum to the PCI Local Bus Specification.
Can be configured to be software-compatible with the Alliance Semiconductor SP1011.
Supports daisy-chaining up to 31 devices. The bandwidth is shared among the devices using a fairness algorithm.
Programmable interrupt controller with up to 10 interrupts per PCI-X port.
- Built-in two-level PCI-X arbiter with support for up to 6 devices.
- Also supports external arbiter.
- Transaction forwarding for the following commands:
- All I/O and memory commands.
- Type 1 to Type 1 configuration commands (downstream only).
- Type 1 to Type 0 configuration commands (downstream only).
- Internal buffers to support high-speed operation, including:
- 1536-bytes HT forwarding (512 bytes each for posted, non-posted and response).
- Following buffers are supported for each PCI-X port:
- 1024-bytes upstream write (posted).
- 2048-bytes upstream read (non-posted), among up to four outstanding requests.
- 512-bytes downstream write (posted).
- 512-bytes downstream read (non-posted).
- 64-bit memory mapped space and 25-bit I/O space.
- 64-bit Address Remapping (downstream) and one DMA Window (upstream).
- Full UnitID Clumping support.
- Supports 64-bit Address Extension.
- Evaluation board available with firmware and software drivers (Q1 2004).
- 6 watts maximum power consumption.
- Optional 5V tolerant PCI I/O in Conventional PCI mode when operating at 25 or 33 MHz.
- 388-pin HSBGA package.
Applications:
- High-end computing systems
- Computer Servers
- Server clusters
- Workstations
- Desktop PCs
- Storage systems and switches (SAN, NAS, RAID, FC)
- Printing, graphics, and imaging Systems
- VPN switches and routers
- Edge and access routers
- Wireless gateways
- Voice and multimedia access gateways
- IP service switches and core routers
- Test equipment and network probes
- Embedded systems
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