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Flexible & Versatile PCI Express Switch


PLX Technology

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The ExpressLaneTM PEX 8524 device offers PCI Express switching capability enabling users to add scalable high bandwidth, non-blocking interconnection to a wide variety of applications including servers, storage systems, communications platforms, blade servers, and embedded-control products. The PEX 8524 is well suited for fan-out, aggregation, dual-graphics, peer-to-peer, and intelligent I/O module applications. The ExpressLane PEX 8524 offers highly configurable ports. There are a maximum of 6 ports that can be configured to any legal width from x1 to x16, in any combination to support your specific bandwidth needs. The ports can be configured for symmetric (each port having the same lane width and traffic load) or asymmetric (ports having different lane widths) traffic. In the event of asymmetric traffic, the PEX 8524 features a flexible central packet memory that allocates a memory buffer for each port as required by the application or endpoint. This buffer allocation along with the device's flexible packet flow control minimizes bottlenecks when the upstream and aggregated downstream bandwidths do not match (are asymmetric). Any of the ports can be designated as the upstream port, which can be changed dynamically. The PEX 8524 provides end-to-end CRC protection (ECRC) and Poison bit support to enable designs that require end-to-end data integrity. These features are optional in the PCI Express specification, but PLX provides them across its entire ExpressLane switch product line. The ExpressLane PEX 8524 product supports full non-transparent bridging (NTB) functionality to allow implementation of multi-host systems and intelligent I/O modules in communications, storage, blade server, and graphics fan-out applications. To ensure quick product migration, the non-transparency features are implemented in the same fashion as in standard PCI applications. Non-transparent bridges allow systems to isolate memory domains by presenting the processor subsystem as an endpoint, rather than another memory system. Base address registers are used to translate addresses; doorbell registers are used to send interrupts between the address domains; and scratchpad registers are accessible from both address domains to allow inter-processor communication. The ExpressLane PEX 8524 switch supports 2 full-featured Virtual Channels (VCs) and a full 8 Traffic Classes (TCs). The mapping of Traffic Classes to port-specific Virtual Channels allows for different mappings for different ports. In addition, the devices offer user-selectable Virtual Channel arbitration algorithms to enable users to fine tune the Quality of Service (QoS) required for a specific application. The PEX 8524 provides low power capability that is fully compliant with the PCI Express power management specification. In addition, the SerDes physical links can be turned off when unused for even lower power.
  • 24-lane PCI Express switch
  • Integrated SerDes
  • Up to six configurable ports
  • 31mm x31mm, 644 pin PBGA package
  • Typical Power: 3.9 Watts
  • PCI Express Base Specification, r1.1
  • Non-blocking switch fabric
  • Full line rate on all ports
  • Configurable Non-Transparent port for Multi-Host or Intelligent I/O Support
  • Six highly flexible & configurable ports (x1, x2, x4, x8, or x16)
  • Configurable with strapping pins, EEPROM, or Host software
  • Lane and polarity reversal
  • Link power management states: L0, L0s, L1, L2/L3 Ready, and L3
  • Device states: D0 and D3hot
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