The ExpressLane PEX 8547 device offers PCI Express switching capability conforming to the latest revision of the PCI Express Base specification (r1.1). This device enables users to add scalable high bandwidth, non-blocking interconnects to high-end graphics applications. The PEX 8547 is designed to support graphics or data aggregation while supporting peer-to-peer traffic for high resolution graphics applications.
The ExpressLane PEX 8547 architecture supports packet cut-through with a latency of 110ns (x16 to x16). This, combined with large packet memory (256 to 1024 byte maximum payload size) and nonblocking internal switch architecture, provide full line rate on its ports for performance hungry applications such as storage servers or storage switch fabrics.
The PEX 8547 supports packet cut-through with a latency of 110ns between symmetric (x16) ingress and egress ports. The low latency enables many applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 1024 bytes, enabling the user to achieve even higher throughput.
The ExpressLane PEX 8547 provides low power capability that is fully compliant with the PCI Express power management specification.
The ExpressLane PEX 8547 is designed to be fully compliant with the PCI-SIG specification. Additionally, it supports auto-negotiation, lane reversal, and polarity reversal.
The ExpressLane PEX 8547 provides several ways to configure its operations. The device can be configured through strapping pins, I2C interface, CPU configuration cycles, or an optional serial EEPROM. This allows for easy debug during the development phase, performance monitoring during the operation phase, and driver or software upgrade.
