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Flexible & Versatile 4-lane 4-port PCI Express® Switch


PLX Technology

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The ExpressLane™ PEX 8604 device offers PCI Express switching capability enabling users to add scalable high bandwidth non-blocking interconnection to a wide variety of applications including control plane applications, consumer applications and embedded systems. The PEX 8604 is well suited for fan-out, peer-to-peer, and intelligent I/O module applications. The PEX 8604 architecture supports packet cut-thru with a maximum latency of 190ns in x1 to x1 configuration. This, combined with low power consumption and non-blocking internal switch architecture, provides full line rate on all ports for lowpower applications such as consumer and embedded. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a max payload size of 2048 bytes, enabling the user to achieve even higher throughout. The PEX 8604 provides end-to-end CRC protection (ECRC) and Poison bit support to enable designs that require guaranteed error-free packets. PLX also supports data path parity and memory (RAM) error correction as packets pass through the switch. The PEX 8604 supports full non-transparent bridging (NTB) functionality to allow implementation of multi-host systems and intelligent I/O modules in applications which require redundancy support such as select embedded applications. Non-transparent bridges allow systems to isolate host memory domains by presenting the processor subsystem as an endpoint rather than another memory system. Base address registers are used to translate addresses, doorbell registers are used to send interrupts between the address domains, and scratchpad registers are accessible from both address domains to allow inter-processor communication. The PEX 8604 is designed to be fully compliant with the PCI Express Base Specification r2.0 and is backwards compatible to PCI Express Base Specification r1.1 and r1.0a. Additionally each port supports auto-negotiation and polarity reversal. Furthermore, the PEX 8604 is designed for Microsoft Vista compliance. All PLX switches undergo thorough interoperability testing in PLX’s Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure compatibility with PCI Express devices in the market. The PEX 8604 provides several ways to configure its operations. The device can be configured through strapping pins, I2C interface, CPU configuration cycles and/or an optional serial EEPROM. This allows for easy debug during the development phase and functional monitoring during the operation phase.
  • 4-lane PCI Express switch; Integrated 5.0 GT/s SerDes
  • Up to 4 configurable ports
  • 15 x 15mm2, 196-ball PBGA
  • Typical Power: 1.5 Watts
  • PCI Express Base Specification r2.0 (Backwards compatible with PCIe r1.0a/1.1)
  • PCI Power Management Spec r1.2
  • Microsoft Vista Compliant
  • Supports Access Control Services
  • Dynamic link-width control
  • Non-blocking internal architecture
  • Full line rate on all ports
  • Cut-Thru latency: 190ns
  • 2KB max payload size
  • Read Pacing (intelligent bandwidth allocation)
  • Dual Cast
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