From Lattice Semiconductor: Power Management 2.0
Written by Shyam Chandra from Lattice
In this 6 part series we are looking at the challenges of implementing an efficient power management architecture in today’s complex circuit board designs.
Each of the previous solutions we shared comes with many trade-offs, balancing performance, flexibility, and reliability against cost, complexity and design difficulty. As circuit boards grow larger and become more complex, these trade-offs become harder to manage, and the flexibility and controllability of the board power management section suffers. Consequently, board bring-up time increases. We need a new solution that incorporates the best of each of the existing models into a single, flexible, reliable, and inexpensive architecture.
A distributed power management architecture eliminates many of these trade-offs through the use of low-cost analog sense and control (ASC) power management elements. These devices, in conjunction with the already existing CPLDs, enable the implementation of the complete hardware management function such as power and temperature management, as well as control path and housekeeping functions.
Meet the L-ASC10, a hardware management expander with power, thermal, and control path sub-blocks. It can be used in conjunction with control PLDs, such as our low-cost MachXO2 and MachXO3 series, to implement the hardware management function in one circuit board.
The L-ASC10 Remote Sensing and Controlling Element
The L-ASC10 provides three types of analog sense channels:
- 10 voltage sense (nine standard channels and one high voltage channel)
- 2 current sense (one standard voltage and one high voltage)
- 3 temperature sense (two external and one internal)
It also provides 3 types control outputs:
- 9 open drain outputs used to enable DPOLs and APOLs
- 4 MOSFET drivers to enable rails to two or more payload ICs to meet their sequencing requirements
- 4 DACs used to implement trimming and margining functions for APOLs
Each of the analog sense channels is monitored through two independently programmable precision comparators supporting under/over/window-compare monitor functions. The communication between the ASC and the control PLD accomplished through a single 3-wire serial bus (TX/RX/Ck) enables the hardware algorithm logic in the CPLD to reliably read the status of supplies, current and temperature to implement reliable board power management functions.
A Hardware Management System Implemented Using ASCs and MachXO2/3
Using a single serial bus to monitor and control multiple power supplies greatly reduces the number of I/O pins required for the PLD. In a distributed hardware management architecture, the control PLD uses several external ASC devices to monitor supply voltages, and also transmits “Enable”/”Disable” commands to the DC-DC supplies and performs other housekeeping functions.
- Common 3-wire bus requires the minimum number of control PLD I/O pins.
- Simplified PCB traces reduces board congestion.
- The entire system can be implemented in a single design environment (GUI or VHDL/Verilog).
- Highly scalable distributed architecture – one design can be reused to reduce time-to-market.
- Reduced solution-cost through integrated voltage, current and temperature monitoring functions within the ASC.
- Combined functions reduce design time.
- Reduced board debug time through Lattice's standard power debug utilities.
As the complexity of board-level systems continues to grow, designing and debugging of the power management portion of the circuit board have begun to consume a disproportionate share of design effort and BOM costs. Using control PLDs and ASC to implement all of management functions has helped mitigate this "complexity creep", without the increase in cost or time to market.
The new power management methodology: distributed hardware management architecture, which connects a control PLD to low-cost sensing elements through a 3-wire serial high speed link reduces design complexity, board space requirements and BOM costs. This architecture may be implemented with a wide variety of tools, commonly used by analog and digital designers.
Today’s complex ASIC/SOC/CPU power, thermal and control path functions need to be managed in a coordinated way to operate optimally. Traditional solutions built with disparate components are fraught with trade-offs, result in increased design and debug times, and sometimes result in board faults that cannot be repeated and sporadically appear during mass production. This new hardware management system addresses all of the disadvantages found in traditional approaches and provides an optimal solution across wide range of applications making it easy to design, easy to debug and easy to reuse.
Read all blogs from our from our Power Manager series:
- The Quest for the Optimal Power Management Architecture
- Power Management with a Control PLD
- Power Management using a Power Manager IC and Control PLD
- Power Management through PMBus and Control PLD
- Power Management using a Control PLD with on-chip ADC
For Further Reading:
- "Revolutionary Hardware management Solutions", A Lattice Semiconductor White Paper, April 2015
- L-ASC10 Data Sheet
- "Adding Scalable Power and Thermal Management to MachXO using L-ASC10" A Lattice Application Note
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