MachXO3 from Lattice Semiconductor: Futureproof your control PLD and bridging designs

Nov 16, 2017
 

Simplified control PLD design and debug – Don’t trade off features and functionality. Integrate more capabilities into MachXO3 device family with up to 9400 LUTs and 384 I/Os.

Secure and reliable – Protect your designs from malicious attacks using password protection, and mitigate soft errors through the state of the art Soft Error Detection and Soft Error Correction features.

Bridge between multiple 4K sensors and displays – Use high-speed 900 Mbps I/Os to implement MIPI D-PHY, CSI-2 or DSI interfaces.

Watch a video from Lattice

Features

  • Up to 9400 LUTs with up to 384 I/O pins
  • Instant-on 1 ms boot-up with background upgrade, Hitless I/O reconfigure and dual-boot error recovery
  • Available with 3.3/2.5 V core or low power 1.2 V core – including additional options on 9400 LUT devices
  • Non-volatile, MachXO3L includes multi-time programmable NVCM
  • MachXO3LF includes programmable Flash and User Flash Memory (UFM)
  • Available in amazingly small (2.50 x 2.50 mm) WLCSP packages and BGA packages with 0.50 mm and 0.80 mm pitch

Source: http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3.aspx?utm_source=MachXO3-10K



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