Timing 101 from Silicon Labs: The Case of the Jitterier Divided-Down Clock

Oct 24, 2017
 

Written by KG Smith from Silicon Labs

Hello and welcome to the “Clocktoberfest” edition of the Timing 101 blog from Silicon Labs.

Nice weather is starting to arrive here in central Texas. By late September and October we get hints of cooler and less humid days to come. Those of us of German descent, and plenty who are not, may celebrate Oktoberfest or some local variant such as Wurstfest in nearby New Braunfels. So “Happy Clocktoberfest!” from the Timing group.

This month I am going to discuss a very common question that arises when measuring the phase noise and phase jitter of relatively low clock frequencies. All things being equal, we generally expect divided-down lower frequency clocks to yield lower phase noise than higher frequency clocks. Quantitatively, you may recall this as the 20log(N) rule.

However, the 20log(N) rule only applies to phase noise and not integrated phase noise or phase jitter. Phase jitter should generally measure about the same. Further, as we get low enough in frequency we do not find this relation to hold true in actual measurements. So the question this month is - why is that?

The 20log(N) Rule

First, a quick review of the 20log(N) rule for those who may not be familiar with it:

If the carrier frequency of a clock is divided down by a factor of N then we expect the phase noise to decrease by 20log(N). For example, every division by a factor 2 should result in a decrease of phase noise by 20log(2) or about 6 dB.  The primary assumption here is a noiseless conventional digital divider.

Why is this? The output of a practical digital divider is rising and falling edges with the signal at a logic high or low level otherwise. Jitter is presented at the rising and falling edges only. The proportion of jitteriness to each clock cycle is reduced. Our intuition may suggest that if we reduce the number of jittery edges then we reduce the jitter transmitted by the divided down clock. That turns out to be correct.

Formally, this can be written as follows:

20log(N).png

 

 

What About Phase Jitter?

We integrate SSB phase noise L(f) [dBc/Hz] to obtain rms phase jitter in seconds as follows for “brick wall” integration from f1 to f2 offset frequencies in Hz and where f0 is the carrier or clock frequency.

phase jitter.png

 

In practice the quantities involved are small enough for good clocks that the RMS phase jitter, for a 12 kHz to 20 MHz jitter bandwidth, is on the order of 10s to 100s of femtoseconds.

Note that the rms phase jitter in seconds is inversely proportional to f0. When frequency is divided down, the phase noise, L(f), goes down by a factor of 20log(N). However, since the frequency goes down by N also, the phase jitter expressed in units of time is constant. Therefore, phase noise curves, related by 20log(N), with the same phase noise shape over the jitter bandwidth, are expected to yield the same phase jitter in seconds.

An Example

Let’s look at a specific example. As an experiment, I took an Si5345 jitter attenuator, input a 25 MHz clock, and configured it so that I only changed an (internal) output divider by factors of 2 to obtain frequencies running from 800 MHz down to 50 MHz. I then measured the phase noise using an Agilent (now Keysight) E5052B and compared the phase noise and phase jitter for each case. Five runs were averaged and correlated for each frequency. I omitted any spurs for clarity and to simplify the experiment.

Through the magic of MS Paint and use of the “Transparent Selection” feature I am able to overlay all of the E5052B screen caps as follows. (If the runs are identical each time only unique text is obscured.) In the figure below, the traces generally run top to bottom in descending carrier frequency, i.e. 800 MHz, then 400 MHz, etc. on down to 50 MHz. The shapes of the curves are the same except where the curves are compressed at the highest offset frequencies.

Example.png

I then tabulated the measured phase jitter results over the 12 kHz to 20 MHz jitter bandwidth as follows:

Table 1.png

There are two immediate observations we can make from the overlaid plots and the table.

  1. The separation between the curves is close to what we would expect applying the 20log(N) rule until the traces begin to appear compressed toward the 100s of kHz to MHz offset
  2. The RMS phase jitter in fs is approximately the same for 800 MHz down to 200 MHz. However, for the 100 MHz and 50 MHz cases the expected phase jitter is way

Despite the 20log(N) rule, the phase jitter is getting worse as I decrease the output clock frequency, especially below 200 MHz. These lower frequency clocks measure far jitterier than expected. Thus arises the case of the jitterier divided-down clock.  So what’s going on?

Curve compression due to the apparent phase noise floor appears responsible for the differences in the calculated RMS phase jitter. Let’s verify that by comparing the data from 10 kHz to 20 MHz offset for the 800 MHz and 100 MHz cases. All of the spot phase noise data came from the original markers plotted except for the 20 MHz points which were estimated from the screen cap plots. (Note that for a factor of 8 or 23 we would expect a delta of 3 x 6 dB or 18 dB in phase noise.)

Table2.png

Taking just these values and entering them in to the Silicon Labs online Phase Noise to Jitter Calculator we obtain the following.

Table 3.png

Not too shabby for the online calculator considering it only had 5 data points to work with!

Now let’s modify the 100 MHz dataset to remove the higher offset frequency compression as follows. The 18 dB Δ is as would be otherwise expected applying the 20log(N) rule.

Table4.png

Entering the modified values in to the online calculator we add its calculation to the table as highlighted:

Table5.png

This exercise confirms that the curve compression accounts for the significant difference in phase jitter

measured between the 800 MHz and 100 MHz cases.

The Noise Floor

All of the traces flatten or get close to flattening by 20 MHz offset. So, what is the apparent or effective noise floor? Note that in general this will be some RSS (Root Sum Square) combination of the instrument phase noise floor and the DUT’s far offset phase noise. For example, if both the DUT and the instrument had an effective phase noise of –153 dBc/Hz at 20 MHz offset then the RSS result would be 3 dB higher or –150 dBc/Hz.

If the instrument noise floor was well below the DUT's we would expect the spot phase noise at 20 MHz offset to decrease by 6 dB, for every division by a factor of 2, from that measured for the 800 MHz clock. But that is not what happened. See the table and accompanying figure below:

Table 6.png

 Phase Noise.png

The phase noise floor is not varying monotonically which suggest multiple factors may be involved. Reviewing the E5052B specs indicates that the SSB phase noise sensitivity should decrease slightly as the carrier frequency is lowered. Also, far offset phase noise from the DUT (Device Under Test) is typically dominated by the output driver’s phase noise and that’s unlikely to vary in this way. We are most likely running in to a combination of the instrument's "actual" phase noise floor as a function of input frequency plus aliasing on the part of the DUT. The Si5345's frequency divider edges can be regarded as sampling the phase noise of the internal clock presented to the divider. This factor is independent of the instrument. It is understood that aliasing can occur but quantifying the specific contribution due to aliasing can be problematic.

This paper suggests that provided the noise BW of the input signal is > 4 x divider output frequency vthen divided PM (Phase Modulation) noise will degrade via aliasing by 10log[(BW/2v0) +1]. The aliasing described primarily impacts the far offsets where we are interested.

The authors write:

"Aliasing of the broadband noise generally has a much smaller effect on the close-to-carrier noise

because it is typically many orders of magnitude higher than the wideband noise."

In these particular measurements, estimated noise floor degradation for the lowest carrier frequencies are plausible assuming a given BW and instrument noise floor. However, no one solution appears to accommodate all the data. It might require operating the device at the highest output frequency and then employing external dividers and filters to properly sort this out. Perhaps in some future post.

Additional Reading

While this month's post has concentrated on phase noise, it should be noted that divided spurs can be aliased or folded in the same way as the authors cited above discuss. One of my colleagues has demonstrated this also and I recommend his article for further reading.

Conclusion

We have reviewed the impact that a phase noise instrument’s apparent or effective phase noise floor can have on both the phase noise curve and phase jitter measurement of sufficiently low frequency clocks. After you have worked with your DUTs and phase noise equipment for some time you will recognize what a typical phase noise curve will look like, the approximate phase noise floor of the equipment, and what are reasonable expectations for phase jitter. Certainly, for the cases above, we would take have to take phase jitter measurements below 200 MHz with a grain of salt. If in doubt, try a similar configuration at a higher frequency for comparison. You will only miss the secondary phase noise degradation due to any instrument noise floor variation and/or aliasing due to higher division factors.

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Endnotes

1. The derivation here is adapted from a slim but information packed book by Dr. William “Bill” Egan

called Frequency Synthesis by Phase Lock published in 1981. See section 4.5, “Effect of Modulation

of a Divided Signal”, pages 75-76. (There is a later and much expanded edition of this book.) Dr. Egan

has passed on but he was a great engineer, author, and teacher in Silicon Valley. He wrote several

excellent, clear, and precise books on frequency synthesis, PLLs, and RF systems design.

2. A. SenGupta and F.L. Walls, “Effect of Aliasing on Spurs and PM Noise in Frequency Dividers”, 2000

IEEE/EIA International Frequency Control Symposium and Exhibition, pages 541 – 548.

Retrieved from http://tf.boulder.nist.gov/general/pdf/1380.pdf.

3. H. Mitchell, "Perfect Timing: performing clock division with jitter and phase noise measurements", EE

Times, 8/25/2011. Howell's paper covers this topic from a different perspective with some additional

detail using data from the previous generation Si5324. He also demonstrates spur aliasing by mixing the

outputs of separate RF signal generators. Retrieved from

https://www.eetimes.com/document.asp?doc_id=1279033.

Source: http://community.silabs.com/t5/Official-Blog-of-Silicon-Labs/Timing-101-The-Case-of-the-Jitterier-Divided-Down-Clock/ba-p/212985



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