Designing a Clock Tree - 5 Questions to Ask | Symmetry Blog
Written by Tyler Wojciechowicz
Clocks and oscillators run your components and make sure everything is systematic and in order. We all know how important these timing parts are, but because they are so common, oftentimes they are not given much thought compared to the rest of the design.
However, what clock you add to a design is important for maximizing the efficiency of your application. Not all clocks are the same, and finding the right clock could make the difference to your application’s effectiveness and reliability.
It would be a shame to design a fantastically powerful application, only for the timing components to get in the way of the application running at its intended effectiveness.
When designing a clock tree, there are a few factors to consider when determining which clock components to choose from. We’ll look at five common considerations for choosing a clock, based on the form and function of your application.
Here are 5 questions to ask when designing a clock tree:
1. Is it a synchronous or free-running design?
Once the clock inventory has been completed, determine if the required timing architecture is free-running or synchronous.
Free-running applications require independent clocks without any special phase-lock or synchronization requirements. Examples include standard processors, memory controllers, SoCs and peripheral components (e.g., USB, PCI Express switches).
Synchronous systems require continuous communication and network-level synchronization across all associated systems. In these applications, low-bandwidth PLL-based clocks provide jitter filtering to ensure that network-level synchronization is maintained. For example, synchronizing all SerDes (serialization-deserialization) reference clocks to a highly accurate network reference clock (e.g., Stratum 3 or GPS) guarantees synchronization across all system nodes. Examples of synchronous clock trees include Optical Transport Networking (OTN), SONET/SDH, Mobile backhaul, Synchronous Ethernet and HD SDI video transmission
What to consider: Whether the timing architecture is free-running or synchronous determines the type of clock you would use. If the architecture is free-running, a clock generator should be used. If the architecture is synchronous, a jitter attenuating clock should be used. While synchronous systems don’t need to have the same frequency, they do need to have the same phase.
Recommended Products: Silicon Labs’ single and multi-DSPLL jitter attenuators generate any combination of output frequencies from any input frequency with industry-leading jitter performance (100 fs RMS). Based on Silicon Labs’ innovative 4th-generation DSPLL architecture, these devices simplify clock tree design by replacing multiple clocks and oscillators, thereby minimizing BOM count and complexity.
2. What clock frequencies do you need?
Clock generators and clock buffers are useful when several reference frequencies are required and the target ICs are all on the same board or in the same IC or FPGA.
The perceived challenge with clock generators is system layout. Placing a crystal adjacent to its target IC is simple and cheap. On the other hand, routing a clock signal from a clock generator to its target IC might not be as easy, although it can save money. Careful design and other techniques can ensure a centralized clock source provides equal performance. Usually, if four or more clocks are required, designers can save money with a clock generator.
What to consider: Depending on the clock frequency your design requires, you will need to look for a clock generator capable of outputting that frequency. SiLabs clock generators can be programmed using SiLabs ClockBuilder Pro software so that your specific frequencies, outputs, formats and requirements are met. Customers can then order samples of this custom part pre-programmed from the factory and receive them in about 2 weeks.
Recommended Products: The Silicon Labs Si534x series of ultra-low jitter clock generators offer any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL with proprietary MultiSynth fractional synthesizer technology to offer a versatile and ultra low jitter clock generator platform. The highly flexible architecture of a Silicon Labs generator allows a wide range of integer and non-integer related frequencies up to 1028 MHz on 10 differential clock outputs while delivering sub-100-fs RMS phase jitter performance with 0 ppm error. Each clock output can be given its own format and output voltage, enabling the Si5341/40 to replace multiple clock ICs and oscillators with a single device - this is a true “clock tree on a chip.”
3. How many of each frequency do you need?
Clock buffers distribute multiple copies or simple derivatives of an input / reference clock.
The reference clock can derive from a clock generator, XO or a system clock. Clock buffers scale their input clock from 2 to more than 10 outputs. They may include I2C, SPI, or pin-controlled features like signal level and format translation, voltage level translation, multiplexing, and input frequency division. These features save space and cost by eliminating components, voltage dividers and signal level transition circuits.
What to consider: Keeping in mind how many outputs your design will require, look for a buffer using Silicon Lab’s product selector to match your # of outputs (or greater), output format, and jitter requirements.
Recommended products: The Silicon Labs Si533xx series of any format, lot-jitter clock buffers and level translators delivers multiple output clock formats from any input clock format. The flexibility of their clock buffers reduces bill of materials complexity by allowing the same device to be used across multiple projects and platforms.
Clock formats supported by this family include LVDS, LVPECL, CML, LVCMOS, SSTL, HCSL, and HSTL.
4. What jitter performance is required on each clock?
Jitter performance varies across a wide range of conditions including
- Device configuration
- Operating frequency
- Signal format
- Input clock slew rate and jitter
- Power supply and power supply noise
Jitter is the deviation in time from an ideal reference clock in the time domain and is a critical specification of timing components. If not addressed, excessive clock jitter can compromise system performance. There are three common types of clock jitter. Depending on the application, one type of jitter may be more important than the others.
- Cycle-to-cycle jitter measures the maximum change in the clock period between any two adjacent clock cycles, typically measured over 1,000 cycles.
- Period jitter is the maximum deviation in clock period with respect to an ideal period over a large number of cycles (10,000 is typical).
- Phase jitter is the figure of merit for high-demanding, high-speed SerDes applications. It is a ratio of noise power to signal power calculated by integrating the clock single-sideband phase noise across a range of frequencies offset from a carrier signal.
What to consider: The total clock tree jitter should be estimated to determine if there is sufficient system-level design margin before the clock tree is committed. A component with poor clock performance can compromise the whole system’s performance if its jitter is too high or poorly specified. It is fundamentally important to note that a clock tree’s jitter is not simply the sum of the MAX specifications of each component; it is the root of the sum of the squares of each device’s MAX RMS jitter.
See Silicon Labs’ phase noise to jitter calculator tool here: https://www.silabs.com/tools/Pages/phase-noise-jitter-calculator.aspx
Recommended products: Silicon Labs’ PCIe clock buffers offer a portfolio of low-power fanout and zero-delay buffers that meet PCI-Express Gen1/2/3/4 specifications. The family is ideal for consumer, industrial, server, storage, and data center applications requiring a high number of PCI-Express clocks.
Their clock buffer devices feature low-power, push-pull output buffer technology, providing benefits of low-power consumption, reduced external terminating resistors, and small packaging.
5. What signal format level is needed for each clock?
Clocks and buffers come in an array of different formats, the following is a description of each:
- Fan out – Fan out is a term that defines the maximum number of digital inputs that the output of a single logic gate can feed. Most transistor-transistor logic ( TTL ) gates can feed up to 10 other digital gates or devices. Thus, a typical TTL gate has a fan-out of 10.
- LVPECL – LVPECL stands for Low-Voltage Positive Emitter-Coupled Logic, and it is a power optimized version of PECL or Positive Emitter-Coupled Logic. It uses a positive 3.3 V power supply.
- LVDS – LVDS is Low-Voltage Differential Signaling, and it is only a physical layer specification, but a data link layer is often added by communication standards and applications.
- CML – Current Mode Logic transmits data at speeds between 312.5 Mbit/s and 3.125 Gbit/s across standard circuit boards.
- HCSL – High-Speed Current Steering Logic is differential logic with two output pins that switch between 0 and 14 mA.
- LVCMOS – LVCMOS stands for Low Voltage Complementary Metal Oxide Semiconductor, and its goal is to reduce the device geometries of integrated circuits, with resulting reduction in operating voltage.
What to consider: Use the format that corresponds to your design and your requirement. Each of the above timing parts come in many different formats to conform to different types of designs.
Why we recommend Silicon Labs
Silicon Labs offers clocks that fit all different needs for your application. As the leader in high-performance clocks and oscillators, Silicon Labs offers the most frequency flexibility for clocks and the industry’s lowest jitter. Their best-in-class integration for single IC clock trees makes design a breeze, and Silicon Labs offers highly programmable clock samples in 1-2 weeks.
Next time you find yourself designing a clock tree, ask yourself these five questions to make sure you are choosing the right clock for your design.
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