From Lattice Semiconductor: "Mobile-Influenced FPGAs Going Broad"
Written by Hussein Osman from Lattice
The complexity of implementing intelligent Edge solutions is causing many issues for designers, including accommodating devices with new and legacy interfaces in a variety of applications. Some of these applications also require compute engines capable of processing data collected at low power and cost.
As a system designer, I worked with FPGAs for years - the type of FPGAs that are capable of implementing a whole processor and peripheral subsystem to validate IPs before taping out a chip. Same FPGAs are used to implement network processors in routers and switches. These FPGAs cost thousands of dollars and consume watts of powers. The iCE40 UltraPlus FPGA offer solutions for connectivity and computing at low cost and high power-efficiency. If you are looking to invent a solution that requires high parallel computation and are looking for a single device with DSP capabilities, amble memory and flexible I/Os, look into the iCE40 UltraPlus FPGA.
This generation of FPGAs has 3K- 5K LUTs, consumes under 100uA in static mode of operations and 1-10mA while ‘on.’ The device is capable of communicating with a wide variety of interfaces – from DSI lane to drive display, VGA parallel camera interfaces and digital microphone inputs to standard I2C, SPI, I2S and UART. With this variety of inputs/outputs designers can drive, interface and process data from many sensor types. This device offers an attractive architecture, low power consumption, integrated PLL, memory and DSPs at size as small as 2.5 mm x 2.5 mm.
IoT devices today have many different sensor types to make sense of the environment around them. Some sensor types can produce a lot of data, even when idle, causing the devices to constantly consume power. This large number of sensors requires innovative sensor-fusion and buffering solutions. Designers need to capture, aggregate, encrypt, buffer, pre-process and time stamp data. In factory automation, industrial test equipment and security camera applications, the iCE40 UltraPlus has the right amount of I/Os, internal resources and LUTs to customize a solution.
In systems with subsystems or multiple PCBs, interconnectivity is done by expensive, failure-prone connectors that let in dirt and water, or expensive flex cables that act as antennas and transmit EMI to the rest of the system. The iCE40 UltraPlus solves this problem with signal aggregation and de-aggregation applications. The device can aggregate data from different interfaces, serialize it into single wire at speeds of up to 8Mbps and de-aggregate the information for distribution, resulting in simplified system design and water-proof, dust-free products. Such conditions are especially desired in the sterile medical environment, as well as many other applications where water entering the system can damage the device.
In IoT applications, designers need a low-power, wireless solution to connect edge devices to the cloud. LoRa (Long Range) is one interface gaining traction due to the low cost of transmission. The iCE40 UltraPlus FPGA can be used to implement this low power interface. The device can aggregate, process and buffer data to be transmitted in intervals, and optimize the interface power consumption. By allowing users to continuously collect data and analyze it, LoRa offers users an attractive design option for low power wireless connectivity. Cities such as New York are implementing LoRa to track consumption of resources, monitor environmental data such as pollution, noise and crime reporting and variety of other applications.
In one of my last blogs we discussed the use of neural networks (NNs) to implement a pattern detector, specifically face detection. This design was done using this same device, showing off its wide range of capabilities. Two sets of NNs were implemented, along with RISC-V processor and accelerators in single chip solution. This solution is inspired by applications intended for smart door bells, smart doors and security systems. It offers a best-in-class power consumption of 1mW for always-on, always-aware face detection.
In order to take advantage of the resources in this device, designer need to be knowledgeable in hardware descriptive languages, such as Verlog or VHDL. The Lattice Radiant software tool and a set of examples and IPs are provided to enable the applications above. These IPs include SPI, I2C, I2S and UART to be used in interfacing with different sensors and for aggregation and de-aggregation applications. Lattice Radiant also offers a predictable design convergence with unmatched ease-of-use. It utilizes a unified database, design constraint flow, and timing analysis to ensure predictability of convergence.
Designers that need to quickly evaluate the key connectivity features of the iCE40 UltraPlus FPGA should try Lattice’s iCE40 UltraPlus Breakout Board, a mobile development platform that includes a number of display and image sensors, or the ultra-low cost UPduino Arduino compatible board from Gnarly Grey.
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