The iC-NF device evaluates the signals from an incremental shaft encoder with the A and B data tracks and an index i.e. zero impulse track Z. The mP interface works externally with an 8- or 16-bit data bus; the widths of the internal bus and registers are 16 bit.
For programming, only the L-byte (lower byte DO..7) is relevant in the 8-bit mode; the 16-bit registers are loaded sequentially. In this mode, the H-byte ports (higher byte D8..15) must be pulled up by external resistors.
The device is controlled by two control words which can be written and read. In the status register, the interrupt word locates the cause of the interrupt from the 8 possible sources. An enabled interrupt message is assigned to the output pins INT1 or INT2.
Information on the current condition of the unsynchronised encoder signals and on the rotational direction can be read out from the tachobyte register.
The signal processing produces clock-synchronised signals from the encoder tracks A and B and recognises the rotational direction. A multiplexer at the input allows the A and B signals to be exchanged. The track filter following can be set for clockwise or counter clockwise rotation and consequently it only passes on correct bit patterns. Two filter outputs with cycle durations which are the same as and the half of track A, as well as the unfiltered encoder signals, can be accessed for the revolution capture. A filter also suppresses short disturbances of the zero impulse.
Two 16-bit counters are available as a timer for the revolution capture. One counter is permanently active whereas the other one can be preset or read. Filtered or unfiltered input signals can be selected with a multiplexer. The gate time for the clock inputs of the counters can be varied with the programmable predivisor. After an interrupt message via the predivisor output (PDO) the inactive counter can be read out and set again. The counter result is proportional to the revolution. Overflows are also passed on to the interrupt controller.
The position sensing uses variable counter depths from 10 to 16 bits and counts up when running clockwise and down when running counter clockwise; a zero impulse resets the counter. Each edge of the synchronised encoder signal counts (fourfold edge evaluation). Deviation from the preset direction and a reaching of the set target marker are signalled to the interrupt controller. There are two target position registers and two comparators, enabling target markers to be set during drive operation.
Additional supervisor counters for both encoder tracks record the unfiltered A and B signals.
A logic low at the reset input NRES resets all counters and registers and switches all outputs bar the OUTB to tristate. In order to check the input thresholds NRES= LOW is maintained; all inputs are thus OR gated to the OUTB output.
With pin NTEST not connected, the test mode is deactivated by an internal pull-up source (NTEST= HIGH). For NTEST= LOW, the variable 10- to 16-bit counter of the position sensing is divided into four 4-bit counters to reduce the counter depth.
All data inputs are compatible with TTL and CMOS levels. The mP interface is bidirectional with Schmitt trigger inputs. The outputs are CMOS compatible (HCT) and drive 4mA d.c. push-pull with a low saturation voltage.
All inputs and outputs are protected against damage by ESD.
• Evaluation of incremental shaft encoder signals for servo controllers
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