CAS Latency and Frequency
Double data rate architecture: two data transfers per clock cycle.
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
DQS is edge-aligned with data for reads and is center-aligned with data for writes.
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation.
Data mask (DM) for write data.
DLL aligns DQ and DQS transitions with CK transitions.
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS.
Burst lengths: 2, 4, or 8
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
8192 refresh cycles / 64ms (4 banks concurrent refresh)
2.5V (SSTL_2 compatible) I/O
Industrial operating temperature range: -40C to +85C for -U series.
Available Lead Free packaging
All Pb-free (Lead-free) products are RoHS compliant