Single-Chip 5-Port 10/100/1000M Switch Controller

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The RTL8367N-CG is a QFN88, high-performance 5-port 10/100/1000M Ethernet switch with an integrated low-power 5-port Giga-PHY that supports 1000Base-T, 100Base-TX, and 10Base-T.

The RTL8367N integrates all the functions of a high-speed switch system; including SRAM for packet buffering, non-blocking switch fabric, and internal register management into a single CMOS device. Only a 25MHz crystal is required; an optional EEPROM is offered for internal register configuration.

The embedded packet storage SRAM in the RTL8367N features superior memory management technology to efficiently utilize memory space. The RTL8367N integrates a 2K-entry look-up table with a 4-way XOR Hashing algorithm for address searching and learning. The table provides read/write access from the EEPROM Serial Management Interface (SMI), and each of the entries can be configured as a static entry. The entry aging time is between 200 and 400 seconds. Eight Filtering Databases are used to provide Independent VLAN Learning and Shared VLAN Learning (IVL/SVL) functions.

The RTL8367N supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on egress. When using this function, VID information carried in the VLAN tag will be changed to PVID.

The RTL8367N supports standard 802.3x flow control frames for full duplex, and optional backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the availability of system resources, including the packet buffers and transmitting queues. The RTL8367N supports broadcast/multicast output dropping, and will forward broadcast/multicast packets to non-blocked ports only. For IP multicast applications, the RTL8367N supports IPv4 IGMPv1/v2 and IPv6 MLDv1 snooping.

In order to support flexible traffic classification, the RTL8367N supports 64-entry ACL rule check and multiple action options. Each port can optionally enable or disable the ACL rule check function. The ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value in 802.1q/Q tag, and rate policing. The rate policing mechanism supports from 8Kbps to 1Gbps (in 8Kbps steps).

In Bridge operation the RTL8367N supports 16 sets of port configurations: disable, block, learning, and forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol. To meet security and management application requirements, the RTL8367N supports IEEE 802.1x Port-based/MAC-based Access Control. For those ports that do not pass IEEE 802.1x authentication, the RTL8367N provides a Port-based/MAC-based Guest VLAN function for them to access limited network resources. A 1-set Port Mirroring function is configured to mirror traffic (RX, TX, or both) appearing on one of the switch’s ports. Support is provided on each port for multiple RFC MIB Counters, for easy debug and diagnostics.

To improve real-time or multimedia networking applications, the RTL8367N supports eight priority assignments for each received packet. These are based on (1) Port-based priority; (2) 802.1p/Q VLAN tag priority; (3) DSCP field in IPv4/IPv6 header; and (4) ACL-assigned priority. Each output port supports a weighted ratio of eight priority queues to fit bandwidth requirements in different applications. The input bandwidth control function helps limit per-port traffic utilization. There is one leaky bucket for average packet rate control for each queue of all ports. Queue scheduling algorithm can use Strict Priority (SP) or Weighted Fair Queue (WFQ) or mixed.

The RTL8367N provides a 4K-entry VLAN table for 802.1Q port-based, tag-based, and protocol-based VLAN operation to separate logical connectivity from physical connectivity. The RTL8367N supports four Protocol-based VLAN configurations that can optionally select EtherType, LLC, and RFC1042 as the search key. Each port may be set to any topology via EEPROM upon reset, or EEPROM SMI Slave after reset.

In router applications, the router may want to know the input port of the incoming packet. The RTL8367N supports an option to insert a VLAN tag with VID=Port VID (PVID) on each egress port. The RTL8367N also provides an option to admit VLAN tagged packets with a specific PVID only. If this function is enabled, the RTL8367N will drop all non-tagged packets and packets with an incorrect PVID.


  • Single-chip 5-port 10/100/1000M non-blocking switch architecture
  • Embedded 5-port 10/100/1000Base-T PHY
  • Each port supports full duplex 10/100/1000M connectivity (half duplex only supported in 10/100M mode)
  • Full-duplex and half-duplex operation with IEEE 802.3x flow control and backpressure
  • Supports 9216-byte jumbo packet length forwarding at wire speed
  • Realtek Cable Test (RTCT) function
  • Supports 64-entry ACL Rules
    • Search keys support physical port, Layer2, Layer3, and Layer4 information
    • Actions include mirror, redirect, dropping, priority adjustment, traffic policing, CVLAN decision, SVLAN assignment, interrupt and logging counter
    • Supports five types of user defined ACL rule format for 64 ACL rules
    • Optional per-port enable/disable of ACL function
    • Optional setting of per-port action to take when ACL mismatch
  • IEEE 802.1Q VLAN
    • Supports 4K VLANs and 32 Extra Enhanced VLANs
    • Supports Un-tag definition in each VLAN
    • Supports VLAN policing and VLAN forwarding decision
    • Port-based, Tag-based, and Protocol-based VLAN
    • Up to 4 Protocol-based VLAN entries
    • Per-port and per-VLAN egress VLAN tagging and un-tagging
  • Supports IVL, SVL, and IVL/SVL
    • 2K-entry MAC address table with 4-way hash algorithm
    • Up to 2K-entry L2/L3 Filtering Database
    • Per-port MAC learning limitation
  • Spanning Tree port behavior configuration
    • IEEE 802.1w Rapid Spanning Tree
    • IEEE 802.1s Multiple Spanning Tree with up to 16 Spanning Tree instances
  • IEEE 802.1x Access Control Protocol
    • Port-Based Access Control
    • MAC-Based Access Control
    • Guest VLAN
  • Supports Auto protection from Denial-of-Service attacks
  • H/W IGMP/MLD Snooping
    • IGMPv1/v2 and MLD v1
    • Supports ‘Fast Leave’
    • Static router port configuration
    • Dynamic router port learning and aging
  • Quality of Service (QoS)
    • Supports per-port Input Bandwidth Control
    • Eight Priority Queues per port
    • Per queue flow control
    • Traffic classification based on IEEE 802.1p/Q priority definition, physical Port, IP DSCP field, ACL definition, VLAN based priority, MAC based priority, and SVLAN based priority
    • Min-Max Scheduling
    • Strict Priority and Weighted Fair Queue (WFQ) to provide minimum bandwidth
    • One leaky bucket to constrain the average packet rate of each queue
  • Supports rate limiting (64 shared meters, with 8kpbs granulation)
  • RFC MIB Counter
    • MIB-II (RFC 1213)
    • Ethernet-Like MIB (RFC 3635)
    • Interface Group MIB (RFC 2863)
    • RMON (RFC 2819)
    • Bridge MIB (RFC 1493)
    • Bridge MIB Extension (RFC 2674)
  • Stacking VLAN and Port Isolation with eight Enhanced Filtering Databases
  • IEEE 802.1ad Stacking VLAN
    • Supports 64 SVLANs
    • Supports 32 L2/IPv4 Multicast mappings to SVLAN
    • Supports MAC-based 1:N VLAN
  • Supports two IEEE 802.3ad Link aggregation port groups
  • Port Mirror function for one source port to multiple destination ports
  • OAM and EEE LLDP (Energy Efficient Ethernet Link Layer Discovery Protocol
  • Loop Detection
  • Security Filtering
    • Disable learning for each port
    • Disable learning-table aging for each port
    • Drop unknown DA for each port
  • Broadcast/Multicast/Unknown DA storm control protects system from attack by hackers
  • Realtek Green Ethernet
    • Link-On Cable Length Power Saving
    • Link-Down Power Saving
  • Each port supports 3 LED outputs
  • Supports EEPROM SMI Slave interface to access configuration register
  • Supports 32K-byte EEPROM space for configuration
  • Integrated 8051 microprocessor
  • Supports Flash Interface
  • 25MHz crystal or 3.3V OSC input
  • QFN 88-pin package

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