CPRI for ECP5-5G - Single Design

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Product Information

This IP core together with SERDES and Physical Coding Sub-layer (PCS) functionality integrated in the LatticeECP3™ and ECP5™ LFE5UM FPGAs implements the physical layer of the CPRI specification and interleaves IQ data with synchronization, control and management information. It can be used to connect Radio Equipment Control (REC) and Radio Equipment (RE) modules.

The CPRI IP core implements not only all of the capabilities required to support the physical layer of the CPRI specification (basic function), but also specific requirements related to link delay accuracy (low latency character).

One CPRI core configuration for 5G version (4.9152 Gbps) is also supported. It is similar to the "low latency" one for 3G version except the data rate. The remainder of this document focuses on the detailed specifications associated with implementing and using the basic function. The LatticeECP3 and ECP5 LFE5UM FPGAs optimize PCS/SERDES architecture for low latency control. Complete details on the implementation and use of the low latency configuration are included in IPUG74, CPRI IP Core Low Latency Variation Design Considerations User’s Guide.

The CPRI soft-core comes with the following documentation and files:
• Data sheet
• Protected netlist/database
• Behavioral RTL simulation model
• Source files for instantiating and evaluating the core

The CPRI IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP core that operate in hardware for a limited period of time (approximately four hours) without requiring the purchase of an IP license. It may also be used to evaluate the core in hardware in user-defined designs. Details for using the hardware evaluation capability are described in the Hardware Evaluation section of this document.

In the following text, transmit refers to data flow from the user application logic to the CPRI link. Receive refers to data flow from the CPRI link to the user application logic. Downlink refers to the direction of data flow from REC to RE, and uplink refers to the direction of data flow from RE to REC.

The Lattice CPRI core is compliant with the version 5.0 CPRI specification. Note however that the core does not directly support requirement R-31 (line-rate auto-negotiation). For the 3G version, Lattice supports dynamic switching between full and half rate line settings (i.e., 614M/1.2G or 1.2/2.4G). However, switching dynamically between all line rates is not supported since some PCS/SERDES bit settings need to be re-programmed through the SCI to support reliable data transfer. It is anticipated that in most network applications, line rate negotiation will be established/managed at the system level and there is nothing in the IP core that precludes supporting such capability.

Symmetry Electronics is an authorized Lattice Semiconductor distributor.


Supports the physical link layer (Layer 1) of the CPRI specification
Supports three standard bit rates of the CPRI specification
614.4 Mbps
1228.8 Mbps
2457.6 Mbps
3072 Mbps
Supports 8b/10b encoding/decoding performed in the PCS/SERDES
Supports code-violation detection performed in the PCS/SERDES
Performs CPRI Hyper-frame Framing
Performs interleaving of IQ data, sync, C&M data, and vendor specific information
Provides an 8-, 16-, or 32-bit parallel interface for IQ data
Performs sub-channel mapping:
Supports a slow C&M channel based on a serial HDLC interface at standard bit rates (240 Kbps, 480 Kbps,960 Kbps, and 1920 Kbps). The HDLC framer, if needed, must be provided as a separate IP core.
Supports a fast C&M channel based on a serial Ethernet interface (84.48 Mbps max.) to the user logic, anon-standard rate MII Ethernet interface to a MAC, or a 100 Mbps MII interface to a PHY device. Accepts a user-selected pointer to the CPRI sub-channel where the Ethernet link starts. The Ethernet MAC function is provided as a separate IP core.
Performs synchronization and timing as defined in section 4.2.8 of the CPRI Specification
Supports the L1 Inband Protocol
Provides a parallel interface for merging vendor specific data into the CPRI frame
Provides a start-up sequence state machine in hardware for both REC and RE nodes which performs:
Synchronization and Rate Negotiation
C&M Plane set-up
Performs Link Maintenance as defined in section 4.2.10 of the CPRI Specification:
LOS detection
LOF detection
RAI indication
Optional top-level template that implements user registers for control and status management
Optional 8-bit register interface through the JTAG port


Lattice Semiconductor User Guide

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