Wireless Jitter Attenuating Clock Multiplier Development Kit

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The Si5381/82E-E-EB is used for evaluating the Ultra-Low Phase Noise Quad/Dual PLL. The Si5381/82 employs fourth-generation DSPLL technology to enable clock generation for LTE/ JESD204B applications which require the highest level of jitter performance. The Si5381/82E-E-EB has four independent input clocks and a total of 12 outputs with 4 PLLs. The Si5381/82E-E-EB also has four independent input clocks and a total of 12 outputs with 2 PLLs. The Si5381/82E-E-EB can be easily controlled and configured using Silicon Labs’ Clock Builder Pro™ (CBPro™) software tool.

The device revision is distinguished by a white 1 inch x 0.187 inch label with the text “Si5381/82E-E-EB” installed in the lower left hand corner of the board. (For ordering purposes only, the terms “EB” and “EVB” refer to the board and the kit respectively. For the purpose of this document, the terms are synonymous in context.)

Each kit includes:
• Seamless download from ClockBuilder Pro to EVB
• SMA connectors for high quality measurements
• No external clocks are required for free-run evaluation
• Real-time power and junction temperature measurements
• Access all registers, LED indicators and I/O
• Most configurations can be powered by USB

Symmetry Electronics is an authorized Silicon Labs distributor.