WEBINAR from Silicon Labs: 5 Clock Tree Design Techniques


Title: 5 Clock Tree Design Techniques to Optimize 10/25/40/56 Gb/s SerDes Performance for Networking and Data Centers (EMEA)

Date: Wednesday, October 11, 2017

Time: 10:00 AM Central European Summer Time

Duration: 1 hour

As new designs adopt FPGAs, SoCs, ASICs, and CPUs with higher speed SerDes, it’s becoming increasingly important to understand the impact of reference timing on overall system performance. This webinar provides practical guidance on overcoming common timing design challenges by reviewing timing requirements for 10G/25G/40G/56G-based designs, explaining when to use clocks versus oscillators, highlighting system-level factors that degrade signal integrity and reviewing how to budget jitter and/or phase noise margin in order to select an optimal timing solution. This webinar also explains how to use common bench equipment and software-based tools to simplify the design-in process.

REGISTER HERE: http://community.silabs.com/t5/Official-Blog-of-Silicon-Labs/Webinar-5-Clock-Tree-Design-Techniques/ba-p/203430

Contact Symmetry Electronics at 866-506-8829, email us or start a live chat and we'll be glad to help you with your projects!

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